Interconnect Layout Optimization by Simultaneous Steiner Tree Construction and Bu er Insertion

This paper presents an algorithm for interconnect layout optimization with bu er insertion. Given a source and n sinks of a signal net, with given positions and a required arrival time associated with each sink, the algorithm nds a bu ered Steiner tree so that the required arrival time (or timing slack) at the source is maximized. In the algorithm, Steiner routing tree construction and bu er insertion are achieved simultaneously by combining A-tree construction and dynamic programming based bu er insertion algorithms, while these two steps were carried out independently in the past. Extensive experimental results indicate that our approach outperforms conventional two-step approaches. Our bu ered Steiner trees increase the timing slack at the source by up to 75% compared with those by the conventional approaches.